This article has multiple issues. Please help improve it or discuss these issues on the talk page. (Learn how and when to remove these messages) This article may be too technical for most readers to understand. Please help improve it to make it understandable to non-experts, without removing the technical details. (October 2013) (Learn how and when to remove this message) Category:Wikipedia articles that are too technical from October 2013Category:All articles that are too technical This article may rely excessively on sources too closely associated with the subject, potentially preventing the article from being verifiable and neutral. Please help improve it by replacing them with more appropriate citations to reliable, independent sources. (October 2013) (Learn how and when to remove this message) Category:Articles lacking reliable references from October 2013Category:All articles lacking reliable references (Learn how and when to remove this message)

Advanced Synchronization Facility (ASF) is a proposed extension to the x86-64 instruction set architecture that adds hardware transactional memory support. It was introduced by AMD; the latest specification was dated March 2009.^[1] As of October 2013^[update]Category:Articles containing potentially dated statements from October 2013Category:All articles containing potentially dated statements, it was still in the proposal stage.^[2] No released microprocessors implement the extension.

Features

ASF provides the capability to start, end and abort transactional execution and to mark CPU cache lines for protected memory access in transactional code regions. It contains four new instructions—SPECULATE, COMMIT, ABORT and RELEASE—and turns the otherwise invalid LOCK-prefixed MOVx, PREFETCH and PREFETCHW instructions into valid ones inside transactional code regions. Up to 256 levels of nested transactional code regions is supported.

The SPECULATE and COMMIT instructions mark the start and end of a transactional code region. Inside transactional code regions, the LOCK-prefixed MOVx reg/xmm, mem, PREFETCH and PREFETCHW instructions can mark up to four cache lines for protected memory access. Accesses from other processor cores to the protected cache lines result in exceptions, which in turn cause transaction aborts. Stores to protected cache lines must be performed using the LOCK MOVx mem, reg/imm/xmm instructions. Marked cache lines can be released from protection with the RELEASE instruction. Transaction aborts generated by hardware or explicitly requested through the ABORT instruction rolls back modifications to the protected cache lines and restarts execution from the instruction following the top-level SPECULATE instruction.

See also

• Transactional Synchronization Extensions, Intel's competing technology first implemented in Haswell-based microprocessors

References